Honored ContributorI want to know if there is any alternate command for 'set_case_analysis' as this tcl command is not working in altera(time quest). This command is used to constrain a particular pin/port to a particular value when doing timing analysis.
eg: "set_case_analysis 0 port1" This command assigns 0 to port1 in timing analysis. Is there any alternate way to do this in altera?
Honored ContributorTimeQuest doesn't support it. Could you elaborate what you're trying to do and maybe there's another approach?
Honored ContributorTake the example
"set_case_analysis 0 port1" This pin,port1 is a static pin. It wont change for one complete run(but it is not tied to 0). But above all it is in a clock path and not a data path. So i do not need a false path there. This pin is the select line of the mux in the clock path. So i need to constraint this pin to a particular value(0 here) so that only one particular path is taken while analyzing. Since it is in the clock path i cant use false path command. One alternate method i can do is to tie that port to 0 and 1 and do the complete set up(synthesizing, place & route) for both and see if timing is met when tied to 0. But here the problem here is if there are "n" such situations, i will be having 2^n bit maps at the end.Honored ContributorThe alternate method won't work because you'll be analyzing completely different place-and-routes, where you'll really only be running one image.
For clock muxes, the select line can generally come from: - A top-level port - A regisiter - A combinatorial node based off a clock(and perhaps a combination of the previous two) If it comes from a port, then it won't be analyzed as a clock unless you put a clock constraint on it, so you should be fine. If it comes from a register, clocks don't propogate through registers unless you put a generated clock assignment on it, so again, you should be fine. If it comes from a combinatorial node, then the registers/ports upstream from that comb node will not get analyzed as clocks for the reasons above, and I doubt an actual clock would drive directly into the select line of a clock mux(let me know if I'm wrong). I've analyzed numerous clock muxes without this constraint. Please let me know if I'm overlooking something.
