Forum Discussion
Altera_Forum
Honored Contributor
13 years agoTake the example
"set_case_analysis 0 port1" This pin,port1 is a static pin. It wont change for one complete run(but it is not tied to 0). But above all it is in a clock path and not a data path. So i do not need a false path there. This pin is the select line of the mux in the clock path. So i need to constraint this pin to a particular value(0 here) so that only one particular path is taken while analyzing. Since it is in the clock path i cant use false path command. One alternate method i can do is to tie that port to 0 and 1 and do the complete set up(synthesizing, place & route) for both and see if timing is met when tied to 0. But here the problem here is if there are "n" such situations, i will be having 2^n bit maps at the end.