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SMS's avatar
SMS
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7 years ago

Altera Soft LVDS IP core (output not consistent with the input)

I am simulating the Soft LVDS IP core as receiver by passing a bit stream with IP core parameters configured as follows: Power Supply Mode: Dual (for 10M50DAF484C7G) Functional mode: RX Number of ...
IDeyn's avatar
IDeyn
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7 years ago

Hi SMS.

The typical problem than instantiate LVDS SERDES is to confuse between FCO and DCO. Those clocks have different alignment, so SERDES result could be different because of that.

Best regards,

Ivan