Altera SoC: What is "Peripheral FPGA Clocks" for?

Basically you have to create the tristate logic using FPGA resources. I2C assumes that there are pullups on the bus lines so you just have to control when the pin is an input or driving out ground (driving out high is taken care of by the pullup on the bus).

Here is the mapping:

_sda --> this is the input data from the SDA pin

_out_data --> this is the output enable that you should use to drive a logic '0' out of the SDA pin

_scl_in_clk --> this is the input clock from the SCL pin

_clk_clk --> this is the output enable that you should use to drive the SCL pin

So you would need something like this (Verilog.... my VHDL is too rusty):

assign sda_pin = (out_data == 1)? 1'b0 : 1'bZ; // so when the output enable is high drive out a zero, other wise go Hi-Z

assign hps_0_i2c0_sda = sda_pin;

Those peripheral clock settings are used to provide the tools information about the clock rates of the data moving back and forth between the FPGA fabric (and eventually I/O) and the HPS so that the on-chip constraints can be set accordingly. Since cores like the I2C are not parameterizable IP (hard silicon) this is the only way for the user to tell the tools what frequency they plan to operate them at.