altera_reset_synchronizer_int_chain_out

That's not good, your just sweeping issues under the "false path" rug.

You should set a false path between the reset input signal and the synchronization registers _IF_ the reset signal is asynchronous in respect to the target clock.

If you still get failing paths after that, then you have a problem that affects timing and you need to take care of it that way.

Maybe the reset output needs to be driven to a global clock signal and Quartus is failing to do so automatically?