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Honored Contributor
Honored ContributorAltera PLL cascading
Hi. I'm using Cyclone V E. I have 2 PLLs in project. Can I use a pll cascading feature in this FPGA? Why I can't just connect PLL's one output outclk0 with refclk of PLL two? Whe...
Altera_ForumHonored Contributor
Honored ContributorI have the same question here: Why I can't just connect PLL's one output outclk0 with refclk of PLL two? Must I use the cascade_out & adjpllin? what is the difference?
