Altera Nios II, .elf & .sof in one .rbf file

Thanks for the prompt reply. I am currently using a generated script to load my firmware/FPGA:

#  Creating .flash file for the FPGA configuration 
"$SOPC_KIT_NIOS2/bin/sof2flash" --epcs --input="../altera/quartus/ep3c10/project.sof" --output="project.flash" 
#  Programming flash with the FPGA configuration 
"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --epcs --base=0x00000000 --sidp=0x00001838 --id=782884571 --timestamp=1242411783 --instance=0 "project.flash" 
#  Creating .flash file for the project 
"$SOPC_KIT_NIOS2/bin/elf2flash" --epcs --after="project.flash" --input="../altera/nios/app/firmware/firmware.elf" --output="firmware.flash" 
#  Programming flash with the project 
"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --epcs --base=0x00000000 --sidp=0x00001838 --id=782884571 --timestamp=1242411783 --instance=0 "firmware.flash" 
 

i.e I believe it writes the .sof followed by the .elf. I am trying to prepare a single .rbf file from the two to be written to a CPLD. I think this is different to what you are describing? Thanks once again for all the help.

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If all of your code resides in onchip memory, here's the flow you should use:

1. Generate your hardware system in SOPC Builder.

2. Build your software using either the IDE or Software Build Tools flow.

- If using SBT flow, be sure to take the extra step of generating memory initialization files.

3. Compile your design in Quartus II.

- The SOF compilation process should populate your internal memories, properly, and all should "just work".

Cheers,

- Ura

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