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Honored Contributor
Honored ContributorAltera MAX10 enable clock-buffer primitives without synchronization?
Irrespective of the relative evil of gating clocks in FPGAs my understanding was that one should synchronize the enable signal to the clock being gated by means of a flip-flop chain. Ho...
Altera_ForumHonored Contributor
Honored ContributorI understand that there are no two stage registers but I believe the document meant to gate the clock with enable (generated from its domain) as per figure 5
