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Someone can please give me some information about this? What is the speed of this internal oscillator? What I need to do to use it? The result will be the same as using an external clock?
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Here's example code to simulate and synthesize the internal oscillator.
Read the comments in the files for details. For example, src/toggle.vhd
--
-- MAX II CPLDs have a User Flash Memory (UFM) block that
-- includes an oscillator. The nominal frequency of the
-- oscillator is around 18MHz. A divided-by-4 version of the
-- oscillator is available to clock user logic.
-- Reference indicates that the nominal frequency of the
-- user clock signal is 4.4MHz, with a range of 3.3MHz to
-- 5.5MHz (25% variation).
--
Cheers.
Dave
Honored Contributor
