[Altera FPGA block memory] to which port the ASIC chip select (CS) signal be fed

Here I post my own example of probably bad design, related to Altera FPGA block memories. Comments are welcome.

I was prototyping some ASIC RTL on Stratix III FPGA. In the design, there is one memory which I prototyped as FPGA block memories. below is the instantiation code I use. Note that I used clken pin from the RAM megafunction, and I connected chip select (CS) signal of the ASIC RTL to FPGA block memory clken pin.

This proved very bad for timing. TimeQuest timing report complains a very long path that violates timing. This path basically is the path that generates the clken / CS signal. End register of this path is the data_in register of my FPGA block memory (I register wren, data, and address ports of FPGA block memory)

DRAM_16384x32    I1 (
    .address ( ags_1 ),
    .byteena ( byteena_1 ),
    .clken ( ~csns_1 ),
    .clock ( clk_m ),
    .data ( dgs_1 ),
    .wren ( ~wens_1 ),
    .q ( dgr_1 )
    );

My colleague suggested that the following code be used. Note that clken port is tied to '1'. And CS signal is used to feed wren port.

This lead to better timing in my design. I don't see violations on timing paths that end at data_in register. And I can see that, the logic that generates CS signal now is on the path that end at wren register, but doesn't lead to timing violation.

DRAM_16384x32    I1 (
    .address ( ags_1 ),
    .byteena ( byteena_1 ),
    .clken ( 1'b1 ),
    .clock ( clk_m ),
    .data ( dgs_1 ),
    .wren ( ~wens_1 && ~csns_1 ),
    .q ( dgr_1 )
    );

I don't think i can generalize what I see here. Connecting your CS signal to FPGA block memory clken port may not cause any timing problem at all in your design. But to me, this example will make me think again next time I need to instantiate a block memory. Mostly likely i will generate a block memory without clken port at all, and I will feed CS signal to wren port.