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- SyafieqS
Super Contributor
Hi Tom,
Did you manage to work on this? Any update on the issue?
Hello all,
I'm using QuestaSim to examine my IP realization.
Not all internal wires and register (shown in the RTL viewer) can be examined by the verification tool. How can I "ask" the verification tool to enable adding specific registers and wires to the wave graphs?
I'm using Quartus 18.1.
Thanks,
Tom
Hi Tom,
Did you manage to work on this? Any update on the issue?