New ContributorI am supplying this CPLD from two separate power rails (A 1.8V rail and a 3.3V rail). The CPLD uses 1.8V for VCCINT and VCCI02, and uses the 3.3V rail for VCCI01. The 1.8V rail starts up in about 1ms, and the 3.3V rail starts up in about 20-40ms. Will the component have issues since the two supplies are not coming up to voltage simultaneously?
Regular ContributorHi Liam,
Thank you for reaching out to Intel FPGA Community.
To answer your question, MAX V devices allow the device core and I/O blocks to be powered-up with separate supply voltages. . The VCCINT pins supply power to the device core and the VCCIO pins
supply power to the device I/O buffers.
When VCCIO and VCCINT are supplied from different power sources to a MAX V
device, a delay between VCCIO and VCCINT may occur. Normal operation does not
occur until both power supplies are in their recommended operating range. When
VCCINT is powered-up, the IEEE Std. 1149.1 JTAG circuitry is active. TMS and TCK are
connected to VCCIO and if VCCIO is not powered-up, the JTAG signals are left floating.
Thus, any transition on TCK can cause the state machine to transition to an unknown
JTAG state, leading to incorrect operation when VCCIO is finally powered-up. To
disable the JTAG state during the power-up sequence, pull TCK low to ensure that an
inadvertent rising edge does not occur on TCK.
New ContributorThank you for the help! One more question: The 1.8V rail (feeding VCCINT) comes up to voltage in about 300-900 microseconds. The data sheet for the CPLD does not state any voltage rise-time requirements. Is the given range ok for proper operation of the CPLD?
Regular ContributorHi Liam,
In the MAX V Device Handbook, under Power-Up Timing topic (page 3-9), it stated that the amount of time required from minimum value VCCINT (1.55V) to enters user mode is 200 microseconds for 5M40ZE64C4. You can refer to Figure 4-5 (page 4-6) for better understanding of power up characteristics of this device.
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