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1) i have a differential clock on my board which i need to use as the single ended ref clock for my design. which megafunction or altera primitive should i use for converting the differential clock into a single ended clock?
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Generally you don't need any, you can just have a verilog top file that has an input port and an output port. The IO standard determines if it is single ended or differential.
However, with that being set, using a PLL and the dedicated PLL clock output pins will provide better latency control and jitter performance. Use the PLL megawizard to generate your PLL, and make sure you hook up the correct PLL's input and output pins in the pin planner.
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2) should i use altera GPIO megafunction from the IP library catalog or should i use some primitive?
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Don't need this, the synthesis tool and pin planner information will do it for you (At least for the clock).
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3) most of the tutorials online suggest making a .bdf file. however the designs i work with are large so making .bdf files may not be straightforward for my deisgns. is making the .bdf file necessary or can this step be skipped?
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Stick with VHDL or Verilog. .BDF is for beginners or CPLD users that have small designs.
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4) since i've mostly used xilinx FPGAs and in that we have primitives like ibufgds, ibufg etc. for i/o buffering, differential buffering etc. is there some way of finding the altera equivalent of these io buffers/primitives?
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Although the primitives exist, I have not found a need to use them with altera unless you are doing very special clock gating. The tool does a good job.
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5) is it possible to port .edf files (generated by synopsys - synthesis) into quartusII?
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Yes, It see's *.EDF and *.EDIF as design files, but I've never used this.. In my experience, where Simplicity was almost a requirement for Xilinx for many years, Altera did a good enough job that it wasn't required.
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6) xilinx ISE puts IO buffers for all the IOs in the top level of the design. can the same be expected from quartusII or do we have to instantiate IO buffers for the IOs in the top level specifically?
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You can do this, but most of the IO requirements are handled in the pin planner. So you can keep the IO's as simple Verilog/VHDL ports, versus specifying specific IO buffers. That being said, if you are going to an ASIC, the ASIC flow will usually require the IO buffers at the top. What I do in this case is make a simple wrapper that has pure Verilog IO buffer structure that has an ifdef for ASIC synthesis with the ASIC library io buffer.
Pete
Honored Contributor
