Honored ContributorHello;
In my design, I inferred a register with a clk-enable signal, but in the fitter report I found that this a high fan-out signal and affect the system critical path. Can i solve this problem with the Altera Assignment editor.
Honored Contributorwell, what do you want to know?
Honored ContributorHow can I use the assignment editor to reduce the fan-out for this signal.
Honored ContributorI don't know if you can, maybe someone else does.
Honored ContributorHonored ContributorHonored ContributorYou can also do register duplication in the source code. Create two signals assigned from the same source, but each one has a different destination. Then apply the nomerge attribute to them to prevent the synthesis from merging them.
Honored Contributor
