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Honored Contributor
Honored ContributorAltera Assignment problem
Hello;
In my design, I inferred a register with a clk-enable signal, but in the fitter report I found that this a high fan-out signal and affect the system critical path. Can i solve this problem with the Altera Assignment editor.7 Replies
Altera_Forumwell, what do you want to know?
- Altera_Forum
How can I use the assignment editor to reduce the fan-out for this signal.
- Altera_Forum
I don't know if you can, maybe someone else does.
- Altera_Forum
- Altera_Forum--- Quote Start --- this post may be helpful for you http://www.alteraforum.com/forum/showthread.php?t=50587&p=208266#post208266 (http://www.alteraforum.com/forum/showthread.php?t=50587&p=208266#post208266) --- Quote End --- Thanks. I got it.
- Altera_Forum
You can also do register duplication in the source code. Create two signals assigned from the same source, but each one has a different destination. Then apply the nomerge attribute to them to prevent the synthesis from merging them.
- Altera_Forum--- Quote Start --- You can also do register duplication in the source code. Create two signals assigned from the same source, but each one has a different destination. Then apply the nomerge attribute to them to prevent the synthesis from merging them. --- Quote End --- Thanks for your attention But I have a question. In my design I have a control register that feed many multiplexers. This register have a high fan-out signals that have a negative effect in the system timing.. I tried the following 1- To assign this register to a global control register ---------------> That results in no effect on timing 2- To make a max-fan-out assignment to it ---------------> The same fan out problem reported in the fitter 3- To select the register duplication in the physical synthesis options --------------> The duplicated registers also reported to have a large fan-out I want a solution for this problem. The Design assistant only advice to solve this problem. What can I do
