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Altera_Forum
Honored Contributor
10 years agoAltera Assignment problem
Hello; In my design, I inferred a register with a clk-enable signal, but in the fitter report I found that this a high fan-out signal and affect the system critical path. Can i solve this problem ...
Altera_Forum
Honored Contributor
10 years ago --- Quote Start --- You can also do register duplication in the source code. Create two signals assigned from the same source, but each one has a different destination. Then apply the nomerge attribute to them to prevent the synthesis from merging them. --- Quote End --- Thanks for your attention But I have a question. In my design I have a control register that feed many multiplexers. This register have a high fan-out signals that have a negative effect in the system timing.. I tried the following 1- To assign this register to a global control register ---------------> That results in no effect on timing 2- To make a max-fan-out assignment to it ---------------> The same fan out problem reported in the fitter 3- To select the register duplication in the physical synthesis options --------------> The duplicated registers also reported to have a large fan-out I want a solution for this problem. The Design assistant only advice to solve this problem. What can I do