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Altera_Forum
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8 years ago

ALTDDIO_OUT for clock output of chip

Dear all, i have an example FPGA configuration project for a FIFO interface. It is for a Cyclone 5 device and is comprised of a fifo interface, an ALTDDIO_OUT and a pll. The FPGA should act as mas...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Thank you both, perchrc and kaz, for clarifying this issue. It helped to get a bigger picture of this most critical timing stuff and now I now which application notes I have to study.

Kind regards.