Forum Discussion
GLees
Contributor
ContributorALTDDIO_IN Seems Slow
I'm designing a deserializer in Cyclone V and see something strange with a simple ALTDDIO_IN megafunction;
If I leave the clock and data_in ports unassigned the timing analyzer states an Fma...
Nurina
Regular Contributor
Regular ContributorHello,
That is odd, but since the problem has been solved I shall close this case. If you have a new question, please login to https://supporttickets.intel.com , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey
Regards,
Nurina
