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GLees's avatar
GLees
Icon for Contributor rankContributor
3 years ago

ALTDDIO_IN Seems Slow

I'm designing a deserializer in Cyclone V and see something strange with a simple ALTDDIO_IN megafunction; If I leave the clock and data_in ports unassigned the timing analyzer states an Fma...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Please share the .qar file. To generate this, go to Project>Archive Project.

So that I can see what other settings you have applied in the project.


Regards,

Nurina


  • GLees's avatar
    GLees
    Icon for Contributor rankContributor
    3 years ago

    I started to prepare a .qar file by recompiling the project and then ran the timing analyzer one last time. Lo and behold I now get an Fmax around 400Mhz like it should be. I don't know how to explain this. I guess for now the problem is solved.