Forum Discussion
GLees
Contributor
ContributorALTDDIO_IN Seems Slow
I'm designing a deserializer in Cyclone V and see something strange with a simple ALTDDIO_IN megafunction;
If I leave the clock and data_in ports unassigned the timing analyzer states an Fma...
GLeesContributor
ContributorYes, I've assigned physical pins, valid LVDS clock and LVDS input. I see no critical warnings. I'm using version 18.1.0.
Thanks for you response,
Greg
