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Altera_Forum
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15 years ago

ALT2GXB reset sequence without RX Clock

Hello. I'm creating a reset controller for a new design that utilizes the Arria GX transceivers. I'm targeting PCI Express x1. I'm seeing that the rx_pll_locked signal is incorrectly being asserted b...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I am seeing something very similar with SerialLite II on Arria GX. Basically I have nothing coming into the rx lane but the IP core thinks that there is something there. I even get random data coming in on the decoded data output and sometimes the data valid signal is asserted. The other signals (pll lock and company) also behave (intermittently) like something is coming in.

I am using the Arria GX demo board. If I figure out something, I will let you know - this must be ALTGXB-related, which is common to both protocols. I too need to fix this because it throws my state machine off.