Honored Contributori want to use ALT_PLL_RECONFIG ip..
i tried design example but its for stratix family and tool is throwing error https://www.altera.com/support/literature/lit-ip.html thanks in advance
Honored ContributorInstantiate the ALT_PLL_RECONFIG Megafunction within Quartus. It will bring up a series of windows to configure the ip, click on "documentation" for information on how to use it.
Honored ContributorMaybe is not supported on your fpga
Honored ContributorI've used PLL_RECONFIG on a Cyclone IV.
Honored ContributorJust to top up, the Cyclone IV use ALTPLL_RECONFIG IP and the new V series devices ie Cyclone V use Altera PLL Reconfig IP
Honored ContributorUnfortunately there is no shortcut way. You cant just change the device from Stratix --> Cyclone IV, despite being ALTPLL & ALTPLL_Reconfig altogether. You would need to rebuild the design using Cyclone IV.
Anyway, if you rebuilt it in CIV, appreciate if you can attach to this post. Im sure someone else would be needing it too. :)Honored ContributorYes, please provide solution for this irritating bug that I am also facing.
