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Altera_Forum
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12 years ago

ALT_LVDS timing fails for core clock

Hi, I'm using Quartus 13.1 with a Stratix IV GX dev kit. Trying to implement a simple test design for a 6 bit deserialiser using ALT_LVDS Rx. But I'm getting timing errors in a weird pla...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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The reference design that came with it had it disabled? If so, could you file an SR or attach a link to the project? That should not be the case, and is cruel to figure out.

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Yes. Submitted an SR.

Edit : http://www.altera.co.uk/products/devkits/altera/kit-siv-gx.html This kit. The 230 edition.