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Honored Contributor
Honored ContributorALT_LVDS timing fails for core clock
Hi, I'm using Quartus 13.1 with a Stratix IV GX dev kit. Trying to implement a simple test design for a 6 bit deserialiser using ALT_LVDS Rx. But I'm getting timing errors in a weird pla...
Altera_ForumHonored Contributor
Honored ContributorThanks Rysc.
Problem resolved as the 'optimize hold timing' option was not selected in the fitter settings. I checked by opening a fresh golden_top project as well. The hold timing was not selected.. Pretty cruel btw. This is Quartus 13.1 And the Stratix IV Gx development kit. Thanks ZubairLK
