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Honored Contributor
Honored ContributorALT_LVDS timing fails for core clock
Hi, I'm using Quartus 13.1 with a Stratix IV GX dev kit. Trying to implement a simple test design for a 6 bit deserialiser using ALT_LVDS Rx. But I'm getting timing errors in a weird pla...
Altera_ForumHonored Contributor
Honored ContributorHaving mc of 6/5 on this path should not be a problem for the fitter, I am surprised. Your problem also got a bit changed from post to post.
you may try this test: add delay to data path as it is too early relative to clk. you have up to 6 clocks to delay it. but two or 3 clock delays should do (on the fast clk period)
