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Altera_Forum
Honored Contributor
Honored ContributorALT_LVDS timing fails for core clock
Hi, I'm using Quartus 13.1 with a Stratix IV GX dev kit. Trying to implement a simple test design for a 6 bit deserialiser using ALT_LVDS Rx. But I'm getting timing errors in a weird pla...
Altera_ForumHonored Contributor
Honored Contributoryour first post path is reported between rx lvds and fifo input
your last report(i didn't read it) is now different and is about lvds internal path
