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Altera_Forum
Honored Contributor
Honored ContributorALT_LVDS timing fails for core clock
Hi, I'm using Quartus 13.1 with a Stratix IV GX dev kit. Trying to implement a simple test design for a 6 bit deserialiser using ALT_LVDS Rx. But I'm getting timing errors in a weird pla...
Altera_ForumHonored Contributor
Honored ContributorI can see the register clocked by rx_outclk so the reported path does not exist. Clearly wrong reporting unless fitter removes it which I doubt.
hold multicycle must always be 1 less than setup multicycle (for all source sync cases) as this says the launch/latch edges are those aligned with zero relationship so 5 is ok.
