Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorALT_LVDS timing fails for core clock
Hi, I'm using Quartus 13.1 with a Stratix IV GX dev kit. Trying to implement a simple test design for a 6 bit deserialiser using ALT_LVDS Rx. But I'm getting timing errors in a weird pla...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- look at the rtl viewer to see why that path is so. I expect there is no register at outputof lvds --- Quote End --- Its there.. I notice the multicycle for setup is 6 and multicycle for hold is 5. These are done by the megafunction. Should the hold multicycle be 6 too? Here is a screenshot with the RTL.. https://www.alteraforum.com/forum/attachment.php?attachmentid=8457
