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Altera_Forum
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12 years ago

ALT_LVDS timing fails for core clock

Hi, I'm using Quartus 13.1 with a Stratix IV GX dev kit. Trying to implement a simple test design for a 6 bit deserialiser using ALT_LVDS Rx. But I'm getting timing errors in a weird pla...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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look at the rtl viewer to see why that path is so. I expect there is no register at outputof lvds

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Its there..

I notice the multicycle for setup is 6 and multicycle for hold is 5. These are done by the megafunction.

Should the hold multicycle be 6 too?

Here is a screenshot with the RTL..

https://www.alteraforum.com/forum/attachment.php?attachmentid=8457