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Honored Contributor
Honored ContributorALT_LVDS timing fails for core clock
Hi, I'm using Quartus 13.1 with a Stratix IV GX dev kit. Trying to implement a simple test design for a 6 bit deserialiser using ALT_LVDS Rx. But I'm getting timing errors in a weird pla...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I tried that. Same kind of error. Launch clock fast clock at 480Mhz. And latch clock 160MHz.. --- Quote End --- look at the rtl viewer to see why that path is so. I expect there is no register at outputof lvds
