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Altera_Forum
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12 years ago

ALT_LVDS timing fails for core clock

Hi, I'm using Quartus 13.1 with a Stratix IV GX dev kit. Trying to implement a simple test design for a 6 bit deserialiser using ALT_LVDS Rx. But I'm getting timing errors in a weird pla...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I do have an sdc. Define the clock inputs. Set the input delay based on setup and hold times.

And have derive pll clocks in it too.

I'll paste it tomorrow morning from the lab.. But its a simple constraints. Took it from the DDR cookbook from the wiki.

I was wondering if giving LVDS megafunction the fast bitclk as clock input would be better or giving it the slow frameclock is better.. And if that makes it quirky..

Hope this helps.

ZubairLK