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Honored Contributor
Honored ContributorAll stx 2 running on single clk pin(no ppm offset)
Hi Im new to altera FPGAs. I went throughout Stx II handbook but one thing is still not clear to me whether is possible. Can I run the entire device based on one fast PLL whic...
Altera_ForumHonored Contributor
Honored ContributorDriving PLLs from a global clock network and cascading PLLs is basically supported by the Stratix II clock distribution scheme. So it's not generally necessary to supply external clocks to multiple inputs in parallel as required with Cyclone or Cyclone II. But it can achieve better jitter performance and lower delay skew.
The device handbook recommends to use different bandwidth settings with cascaded PLLs to avoid possible lock problems.
