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Altera_Forum
Honored Contributor
Honored ContributorAll stx 2 running on single clk pin(no ppm offset)
Hi Im new to altera FPGAs. I went throughout Stx II handbook but one thing is still not clear to me whether is possible. Can I run the entire device based on one fast PLL whic...
Altera_ForumHonored Contributor
Honored ContributorI haven't tried it, but for the internal of the device it is possible, for reference to other PLL's, it's "Maybe" possible.
Not all Altera families allow input to the PLL's to come from internal global clocks. And all will usually give you a "Jitter" performance warning when doing this. What I would do, is lock down the PLL locations you want to use and at the start of the design, hook up at least the PLL's and external clocks and build it to make sure everything works, and you are "OK" with any warning's given. Pete
