All Purpose sign extension VHDL?

Hi, I was just wondering how it would be possible to make an all purpose sign extension entity in VHDL. So I created this sign extension entity but it will only work if the input is 6 bits long. If I put in an input that was say 3 bits long. It wouldn't work. Is it possible to build a SEXT that doesn't have limitation on input bits?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SEXT5_0 is 
    port ( data_in : in std_logic_vector(5 downto 0);
           data_out : out std_logic_vector(15 downto 0));
end SEXT5_0;
architecture behavioral of SEXT5_0 is 
begin
    process (data_in)
begin
    
    
    data_out(5 downto 0) <= data_in;
    data_out(15 downto 6) <= (15 downto 6 => data_in(5));
end process;     
end behavioral;

Side question how can I assign multiple signals the same input

for example I want to do something like this. Is there a legal syntax or would I have to individually set each signal?

R1, R2, R3 < = x"0000"