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Altera_Forum's avatar
Altera_Forum
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14 years ago

All Purpose sign extension VHDL?

Hi, I was just wondering how it would be possible to make an all purpose sign extension entity in VHDL. So I created this sign extension entity but it will only work if the input is 6 bits long. If...
Altera_Forum's avatar
Altera_Forum
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14 years ago

But why not use the inbuilt function "resize" ??? just a single line of code