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Altera_Forum
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16 years ago

[AHDL] Problem with MUX

I am a newbie to Quartus and AHDL. I have problem with multiplexer 3 in 1 out. When I simulate I get for 0 and 1 signal A, for 2 signal B, for 3 signal C. SUBDESIGN mux_3_8bit_1 ( A, B, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Looks ok to mean - you sure its not a problem elsewhere?

Other than that - Id recommend not using AHDL anymore. Move to VHDL or Verilog instead. AHDL simulation is only supported in the quartus simulator, which wont exist for new versions of quartus.