[AHDL] Problem with MUX

I am a newbie to Quartus and AHDL. I have problem with multiplexer 3 in 1 out. When I simulate I get for 0 and 1 signal A, for 2 signal B, for 3 signal C.

SUBDESIGN mux_3_8bit_1
(
    A, B, C        : INPUT;    -- wejscia 8 bitowe - sygnaly w kodzie BCD
    s                            : INPUT;    -- sygnaly sterujace
    Y                            : OUTPUT;    -- sygnal wyjsciowy
)
BEGIN
    CASE s IS
        WHEN 0 =>    Y = A;
        WHEN 1 =>    Y = B;
        WHEN 2 =>    Y = C;
        WHEN 3 =>    Y = B"00000000";
    END CASE;
END;