Hi I am migrating an existing AHL design from MaxPlus to Quartus environment and I noticed that some of the state machine's states/registers were optimized out. I know that in Verilog, Preserve attribute can be used. Does AHDL has similar/equivalent attributes? Thanks Alan

If they were optimised out, there is probably a reason. It wont have anything to do with the language. I dont know of attributes in AHDL, but you can provide similar attributes directly to registers in the global assignments settings in the project (I dont know about this for Max Plus) Also remember that the synthesisor is improved since max plus 2, so may behave differently. I have had MaxPlus compile things for me that quartus says are illegal. My Guess is poor design in the AHDL combined with a better synthesisor.

PS. Quartus will synthesis AHDL just fine - why the language migration? you are adding a risk of the two not being the same.

Hi Below is the piece of SM in AHDL base_2 :MACHINE WITH STATES (s0_ base_2, s1_ base_2, s2_ base_2, s3_ base_2); int_ff2.clk = h1; int_ff2.d = zoom_a; base_2.clk = !h1; CASE ( base_2) IS WHEN s0_ base_2 => /int2 = vcc; IF int_ff2.q THEN base_2 = s1_ base_2; ELSE base_2 = s0_ base_2; END IF; WHEN s1_ base_2 => /int2 = gnd; base_2 = s2_ base_2; WHEN s2_ base_2 => /int2 = gnd; base_2 = s3_ base_2; WHEN s3_ base_2 => /int2 = vcc; IF int_ff2.q THEN base_2 = s3_ base_2; ELSE base_2 = s0_ base_2; END IF; END CASE; In Quartus simulation, I could not locate "s2_ base_2" , the warning message was Warning: Can't display state machine states -- register holding state machine bit "s2_base_2" was synthesized away

The Quartus software manual tells about HDL synthesis directives --- Quote Start --- The AHDL language does not support the synthesis directives or attributes described in this chapter. --- Quote End --- Sounds like tcl commands respectively settings in the Quartus assignment editor are the only means to achieve what you want.

Do you have sample of tcl command to achieve this?

AHDL equivalent to Preserve in in Verilog | Altera Community

12 Replies

Altera_Forum
Honored Contributor
12 years ago
PS. Quartus will synthesis AHDL just fine - why the language migration? you are adding a risk of the two not being the same.
Altera_Forum
Honored Contributor
12 years ago
If they were optimised out, there is probably a reason. It wont have anything to do with the language.
I dont know of attributes in AHDL, but you can provide similar attributes directly to registers in the global assignments settings in the project (I dont know about this for Max Plus)

Also remember that the synthesisor is improved since max plus 2, so may behave differently. I have had MaxPlus compile things for me that quartus says are illegal.

My Guess is poor design in the AHDL combined with a better synthesisor.

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AHDL equivalent to Preserve in in Verilog

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