Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAHDL equivalent to Preserve in in Verilog
Hi I am migrating an existing AHL design from MaxPlus to Quartus environment and I noticed that some of the state machine's states/registers were optimized out. I know that in Verilog, Prese...
Altera_ForumHonored Contributor
Honored ContributorPS. Quartus will synthesis AHDL just fine - why the language migration? you are adding a risk of the two not being the same.
