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Altera_Forum
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12 years ago

AHDL equivalent to Preserve in in Verilog

Hi I am migrating an existing AHL design from MaxPlus to Quartus environment and I noticed that some of the state machine's states/registers were optimized out. I know that in Verilog, Prese...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

If they were optimised out, there is probably a reason. It wont have anything to do with the language.

I dont know of attributes in AHDL, but you can provide similar attributes directly to registers in the global assignments settings in the project (I dont know about this for Max Plus)

Also remember that the synthesisor is improved since max plus 2, so may behave differently. I have had MaxPlus compile things for me that quartus says are illegal.

My Guess is poor design in the AHDL combined with a better synthesisor.