Agilex5 NSATUS signal behavior at power up.

Hi Asaf,

This is actually documented behavior, and what you're seeing is expected.

The brief ~20 µs falling/rising pulse on nSTATUS after you release nCONFIG high is the device's normal error-status signaling mechanism during configuration. If an error occurs during configuration, nSTATUS is asserted (driven low) for a pulse duration ranging from 0.5 ms to 10 ms. Device Configuration User Guide Agilex™ 5 FPGAs and SoCs However, a sub-millisecond (~20 µs) transient is more likely a normal part of the SDM startup and synchronization handshake rather than a configuration error pulse.

Here's the key thing to understand about nSTATUS behavior on Agilex 5:

Previous device families implement nSTATUS as an open-drain output with a weak internal pull-up resistor. In contrast, Agilex 5 devices use a push-pull (actively driven) output for nSTATUS. Device Configuration User Guide Agilex™ 5 FPGAs and SoCs This is a significant difference from earlier families — the push-pull driver means you can see sharper, more defined transitions.

Typically, the Agilex 5 device updates nSTATUS to match the state of nCONFIG, except in error conditions. For example, following a power-on reset (POR), nSTATUS asserts after nCONFIG asserts. Device Configuration User Guide Agilex™ 5 FPGAs and SoCs

The nSTATUS pin indicates device readiness to initiate FPGA configuration. The configuration source can only change the state of the nCONFIG pin when it has the same value as nSTATUS. When the Agilex 5 device is ready, it drives nSTATUS to follow nCONFIG. Device Configuration User Guide Agilex™ 5 FPGAs and SoCs

Regarding the timing specs that bound this behavior:

nCONFIG low to nSTATUS low: max 400 ms (tCF02ST0). Agilex™ 5 FPGAs and SoCs Device Data Sheet

nCONFIG high to nSTATUS high: max 20 ms (tCF12ST1). Agilex™ 5 FPGAs and SoCs Device Data Sheet

So the SDM has up to 20 ms to bring nSTATUS high after nCONFIG goes high. A brief transient dip during that window — while the SDM is initializing and synchronizing — is consistent with the push-pull driver actively managing the signal state during the SDM startup sequence.

One important note: all dedicated configuration/JTAG, SDM, and SDM optional signal pins are in the undetermined state during device power up and power down. Pin Connection Guidelines This means some transient behavior on nSTATUS during and immediately after power ramp-up is expected before the SDM takes full control.

Also worth confirming on your board: nSTATUS has an internal 20-kΩ pull-up resistor with 8 mA drive strength. Ensure that during power up, no external component drives the nSTATUS signal low. Pin Connection Guidelines And per the design guidelines, pull the nSTATUS pin high to VCCIO_SDM and ensure no external component drives nSTATUS low during power up. Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

Bottom line: The ~20 µs transient you're seeing on nSTATUS after nCONFIG releases high is consistent with normal SDM startup behavior on Agilex 5. As long as nSTATUS settles high within 20 ms of nCONFIG going high and configuration completes successfully (CONF_DONE and INIT_DONE assert), this is not a concern. Altera recommends measuring the configuration time starting from when nSTATUS goes high to when CONF_DONE goes high Device Configuration User Guide Agilex™ 5 FPGAs and SoCs — use that as your primary health indicator.

If you are seeing repeated configuration failures alongside this pulse, then it would be worth checking whether any external component is inadvertently pulling nSTATUS low during that window.