Agilex IBIS Model

We were able to confirm that the silicon creates the same slew rate and waveform as the IBIS model. I would encourage anyone designing memory channels with the Agilex FPGA family to simulate the channel (Intel recommends this also). You basically have two choices for slew rate (the slow slew rate is over 1ns so is completely useless for DDRx channels regardless of operating speed). The medium slew rate has the stair step edges so will create a very interesting eye. While it may have a clear 'center' that might actually pass setup/hold with a bit of margin, that center will be far smaller than if the edges were not stepped. Using the fast slew rate you have a different problem if you're driving anything but an RDIMM with one load. The edge rate will cause reflections off of the DRAM package internal traces which cause resonances along the channel. This collapses the eye at some of the DRAMs regardless of how well you've crafted your PCB and tuned your termination. It's hard to know which is worse, a collapsed eye due to slew rate and stair stepping or a collapsed eye due to reflections. For our discrete channels we will start with the medium slew rate and see how much margin we get. The calibration should help in centering the clock in whatever opening can be found at each DRAM. But if you're just driving RDIMMs, you're all good with the fastest slew rate driver.