Forum Discussion

arik's avatar
arik
Icon for New Contributor rankNew Contributor
3 years ago

Agilex E-TILE CPRI PHY

HI

I use the Intel Agilex FPGA – AGFB014R24B2E2V.

I created the CPRI Phy IP to Line-rate 8 (LR8 (64/66)) and below (LR7 (8/10), LR6 and etc.) – It is not allowed to attache the IP.

When I load the FPGA with the SOF file I can immediately set the line rate to LR8 by setting the CPRI PHY Register 0xC00 to 0x9 (as mentioned in page 320 of the attached UG20160) and it works great (no need even calibration or adaptation).

However, when I want to change the line rate to LR7 by changing the CPRI PHY Register 0xC00 to 0x6 (as mentioned in the UG same page) and changing also the ref_clk to the 153.6 MHz input (changing the phy register 0xEC), the o_sl_rx_ready stays low
no matter if I do calibration, initial/continuous adaptation, reset the Data path, the PMA and/or Rx/Tx PCS or changing PMA attributes such Rx Phase Slip (0x000E to 0x9000), TX/RX Width Mode (0x0014 to 0x0011 or the TX/Rx Channel Divide By Ratio (0x0005 to 0x8120).

Also, when I go back to LR8 – again by changing the CPRI PHY Register 0xC00 to 0x9 and the ref_clk to the 184.32 MHz input – the ready port (o_sl_rx_pcs_ready) stays low.

Another aspect is the Rx Parallel recovered clock (o_rx_clkout2) and the Tx Parallel running clock (o_tx_clkout2).

When I change the line rate from LR8 to LR7 (doing the above steps) the parallel clocks don’t changed from 153.6 MHz (10,137.6 MHz/66) to 491.52 MHz (9,830.4 MHz/20) as expected.

So as I asked before my question is what are the exact steps I should do to change the line rate from LR8 to LR7 and vice versa.

Another thing is that in the UG683860 (Atached page 127 - chp. 4.4.2.1) it is said that in order to make the transition from LR8 to LR7 we need to do the procedure which is described in the c3_reconfig.c file which is in the example design directory (under the Software directory). However, when I created the example design (and I did it several times) the software directory with all its C files was not created.

Can you please send me the example design C files (including th c3_reconfig.c file)?

Best Regards,

Arik

Ubiqam

4 Replies

  • skbeh's avatar
    skbeh
    Icon for Contributor rankContributor
    3 years ago

    Hi Arik

    'When dynamically reconfiguring the PMA to a different data rate, you need to recalibrate the PMA.'

    Suspect your transceivers might not being properly calibrated. You can refer to Chapter 5 about PMA calibration in the E-tile Transceiver PHY IP User Guide.

    https://www.intel.com/content/www/us/en/docs/programmable/683723/current/pma-calibration.html


    5. PMA Calibration

    The PMA is automatically calibrated when it is first enabled. When dynamically reconfiguring the PMA to a different data rate, you need to recalibrate the PMA. The PMA calibration is run when the PMA is enabled after a PMA analog reset, so you perform a PMA analog reset before requesting calibration. Refer to PMA Attribute Details for information on how to change PMA settings using the Avalon memory mapped interface. When referring to the PMA Attribute Codes section of the register map keep the following guidelines in mind:

    • If you change any setting where 'yes' is indicated in the PMA Can be Running While Updating column, ensure that you do not disable the transceiver channel. If you disable the channel, then the transition of disable to enable initiates the

    calibration and causes bit errors.

    • If you change any setting where 'no' is indicated in the PMA Can be Running While Updating column, follow the following flow chart.

    ...

    ...


    Regarding the c3_reconfig.c file, you need to follow the steps in Figure 37 in section 4.1.2, which instantiate the 'E-Tile Dynamic Reconfiguration Suite' and generate the example design.

    Link to '4.1.2. Generating the Design':

    https://www.intel.com/content/www/us/en/docs/programmable/683860/21-3/generating-the-design-41205.html

    I have tried, and the c3_reconfig.c file is generated in ...\software\dynamic_reconfiguration_hardware\c3_reconfig.c


    • arik's avatar
      arik
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi skbeh

      Thanks for your informative answer.

      Regarding the Example design: before, I tried to generate it from the CPRI PHY IP itself and unfortunately it didn't produced the SW directory. However, now I tried the way in the link you suggested and generated the example design with the SW directory. So thanks a lot for that.

      As for the PMA calibration. I tried it before and it didn't help.

      The question is what is the exact procedure (with its the steps, 1 by 1, detailed) to change the line rate from LR8 which is 64/66 decoded (Gearbox 64/66 mode) to LR7 which 8/10 decoded (PMA Direct mode) and vice versa from LR7 to LR8. Should I only change the clock source (between 184.32 MHz and 153.6 MHz) and the CPRI PHY Register 0xC00 (between 0x9 and 0x6) and then do PMA calibration or there are more steps I need to do?

      Best regards,

      Arik

  • skbeh's avatar
    skbeh
    Icon for Contributor rankContributor
    3 years ago

    CPRI under 10G data rate is using soft-PCS and 8b10b interface which does not support RSFEC.

    CPRI above 10G data rate is using hard-PCS and 64b/66b interface with RSFEC.

    So it seem there is a limitation to dynamic reconfiguration between 10.1376 Gbps (LR8) 9.8304 Gbps (LR7).


    In order to verify whether the method you have used to change the line rate is working, you can try change within the same below 10G data rate, i.e. from 9.8304 Gbps to 6.144 Gbps.