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emrahener's avatar
emrahener
Icon for New Contributor rankNew Contributor
3 years ago
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Agilex DDR4 Signal Integrity Simulations Over Shoot - Undershoot Limit and Target Impedance

Hi, We are working on a digital board design with Agilex FPGA and Discrete DDR4 memories. I have made simulations for DQ traces and still working on other connections. Although a 40 Ohm trace i...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hello emrahener,


    Thank you for submitting your question in Intel Community.

    I'm Adzim from Penang Global Application Engineer will assist you in this thread.


    "34 Ohm case seems to have a better performance. Can you comment on this?"

    I have checked your results and I agree with your opinion because the 34 Ohm case has better margin compared to 40 Ohm case.

    The user guide has provided the guideline for user to create the routing for EMIF.

    There are some general requirement that need to follow when doing the routing and it's limit to the trace.

    I believed that the user can perform the simulation to get the optimum result.


    "Since There is some Overshoot up to 1.33881 V and undershoot up to -0.205288V @ FPGA . Can you also provide a limitations for the overshoot -undershoot for FPGA."

    You should be able to find the details in Agilex Device Data Sheet in the Maximum Allowed Overshoot and Undershoot Voltage section.

    Link: https://www.intel.com/content/www/us/en/docs/programmable/683301/current/maximum-allowed-overshoot-and-undershoot.html


    Regards,

    Adzim



AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello emrahener,


Thank you for submitting your question in Intel Community.

I'm Adzim from Penang Global Application Engineer will assist you in this thread.


"34 Ohm case seems to have a better performance. Can you comment on this?"

I have checked your results and I agree with your opinion because the 34 Ohm case has better margin compared to 40 Ohm case.

The user guide has provided the guideline for user to create the routing for EMIF.

There are some general requirement that need to follow when doing the routing and it's limit to the trace.

I believed that the user can perform the simulation to get the optimum result.


"Since There is some Overshoot up to 1.33881 V and undershoot up to -0.205288V @ FPGA . Can you also provide a limitations for the overshoot -undershoot for FPGA."

You should be able to find the details in Agilex Device Data Sheet in the Maximum Allowed Overshoot and Undershoot Voltage section.

Link: https://www.intel.com/content/www/us/en/docs/programmable/683301/current/maximum-allowed-overshoot-and-undershoot.html


Regards,

Adzim