Hi,
I tried to run compilation at the Quartus Prime Pro 22.1.
A lot of pins needs to be removed in the ghrd_agilex_top.vhd, such as (pls look at the commented off ones)
entity ghrd_agilex_top is
port
(
--Additional refclk_bti to preserve Etile XCVR
refclk_bti : in std_logic;
fpga_clk_100 : in std_logic_vector(1-1 downto 0);
fpga_led_pio : out std_logic_vector(4-1 downto 0);
fpga_dipsw_pio : in std_logic_vector(4-1 downto 0);
fpga_button_pio: in std_logic_vector(4-1 downto 0);
FPGA_UART0_RX : in std_logic;
FPGA_UART0_TX : out std_logic;
FPGA_UART1_RX : in std_logic;
FPGA_UART1_TX : out std_logic;
FPGA_RS422_RXD : in std_logic;
FPGA_RS422_TXD : out std_logic;
FPGA_RS422_RE : out std_logic;
FPGA_RS422_DE : out std_logic;
FPGA_TESTIO1 : in std_logic;
FPGA_TESTIO7 : in std_logic;
FPGA_TESTIO8 : out std_logic;
--FPGA_TESTIO2 : in std_logic;
--HPS
-- emif_hps_mem_mem_ck : out std_logic_vector(1-1 downto 0);
-- emif_hps_mem_mem_ck_n : out std_logic_vector(1-1 downto 0);
-- emif_hps_mem_mem_a : out std_logic_vector(16 downto 0);
-- emif_hps_mem_mem_act_n : out std_logic_vector(1-1 downto 0);
-- emif_hps_mem_mem_ba : out std_logic_vector(1 downto 0);
-- emif_hps_mem_mem_bg : out std_logic_vector(1-1 downto 0);
-- emif_hps_mem_mem_cke : out std_logic_vector(1-1 downto 0);
-- emif_hps_mem_mem_cs_n : out std_logic_vector(1-1 downto 0);
-- emif_hps_mem_mem_odt : out std_logic_vector(1-1 downto 0);
-- emif_hps_mem_mem_reset_n : out std_logic_vector(1-1 downto 0);
-- emif_hps_mem_mem_par : out std_logic_vector(1-1 downto 0);
-- emif_hps_mem_mem_alert_n : in std_logic_vector(1-1 downto 0);
-- emif_hps_oct_oct_rzqin : in std_logic;
emif_hps_pll_ref_clk : in std_logic;
-- emif_hps_mem_mem_dbi_n : inout std_logic_vector(9-1 downto 0);
-- emif_hps_mem_mem_dq : inout std_logic_vector(72-1 downto 0);
-- emif_hps_mem_mem_dqs : inout std_logic_vector(9-1 downto 0);
-- emif_hps_mem_mem_dqs_n : inout std_logic_vector(9-1 downto 0);
hps_jtag_tck : in std_logic;
hps_jtag_tms : in std_logic;
hps_jtag_tdo : out std_logic;
hps_jtag_tdi : in std_logic;
hps_sdmmc_CCLK : out std_logic;
hps_sdmmc_CMD : inout std_logic;
hps_sdmmc_D0 : inout std_logic;
hps_sdmmc_D1 : inout std_logic;
hps_sdmmc_D2 : inout std_logic;
hps_sdmmc_D3 : inout std_logic;
hps_emac0_TX_CLK : out std_logic;
hps_emac0_RX_CLK : in std_logic;
hps_emac0_TX_CTL : out std_logic;
hps_emac0_RX_CTL : in std_logic;
hps_emac0_TXD0 : out std_logic;
hps_emac0_TXD1 : out std_logic;
hps_emac0_RXD0 : in std_logic;
hps_emac0_RXD1 : in std_logic;
hps_emac0_TXD2 : out std_logic;
hps_emac0_TXD3 : out std_logic;
hps_emac0_RXD2 : in std_logic;
hps_emac0_RXD3 : in std_logic;
hps_emac0_MDIO : inout std_logic;
hps_emac0_MDC : out std_logic;
hps_uart0_RX : in std_logic;
hps_uart0_TX : out std_logic;
hps_uart1_RX : in std_logic;
hps_uart1_TX : out std_logic;
hps_gpio1_io0 : inout std_logic;
hps_gpio1_io1 : inout std_logic;
hps_gpio1_io4 : inout std_logic;
hps_gpio1_io5 : inout std_logic;
hps_gpio1_io19 : inout std_logic;
hps_gpio1_io20 : inout std_logic;
hps_gpio1_io21 : inout std_logic;
hps_ref_clk : in std_logic
);
end entity;
component qsys_top is
port (
-- wd_reset_reset_n : out std_logic; -- reset_n
-- agilex_hps_f2h_stm_hw_events_stm_hwevents : in std_logic_vector(43 downto 0) := (others => 'X'); -- stm_hwevents
-- agilex_hps_h2f_cs_ntrst : in std_logic := 'X'; -- ntrst
-- agilex_hps_h2f_cs_tck : in std_logic := 'X'; -- tck
-- agilex_hps_h2f_cs_tdi : in std_logic := 'X'; -- tdi
-- agilex_hps_h2f_cs_tdo : out std_logic; -- tdo
-- agilex_hps_h2f_cs_tdoen : out std_logic; -- tdoen
-- agilex_hps_h2f_cs_tms : in std_logic := 'X'; -- tms
-- hps_io_EMAC0_TX_CLK : out std_logic; -- EMAC0_TX_CLK
-- hps_io_EMAC0_TXD0 : out std_logic; -- EMAC0_TXD0
-- hps_io_EMAC0_TXD1 : out std_logic; -- EMAC0_TXD1
-- hps_io_EMAC0_TXD2 : out std_logic; -- EMAC0_TXD2
-- hps_io_EMAC0_TXD3 : out std_logic; -- EMAC0_TXD3
-- hps_io_EMAC0_RX_CTL : in std_logic := 'X'; -- EMAC0_RX_CTL
-- hps_io_EMAC0_TX_CTL : out std_logic; -- EMAC0_TX_CTL
-- hps_io_EMAC0_RX_CLK : in std_logic := 'X'; -- EMAC0_RX_CLK
-- hps_io_EMAC0_RXD0 : in std_logic := 'X'; -- EMAC0_RXD0
-- hps_io_EMAC0_RXD1 : in std_logic := 'X'; -- EMAC0_RXD1
-- hps_io_EMAC0_RXD2 : in std_logic := 'X'; -- EMAC0_RXD2
-- hps_io_EMAC0_RXD3 : in std_logic := 'X'; -- EMAC0_RXD3
-- hps_io_EMAC0_MDIO : inout std_logic := 'X'; -- EMAC0_MDIO
-- hps_io_EMAC0_MDC : out std_logic; -- EMAC0_MDC
-- hps_io_SDMMC_CMD : inout std_logic := 'X'; -- SDMMC_CMD
-- hps_io_SDMMC_D0 : inout std_logic := 'X'; -- SDMMC_D0
-- hps_io_SDMMC_D1 : inout std_logic := 'X'; -- SDMMC_D1
-- hps_io_SDMMC_D2 : inout std_logic := 'X'; -- SDMMC_D2
-- hps_io_SDMMC_D3 : inout std_logic := 'X'; -- SDMMC_D3
-- hps_io_SDMMC_CCLK : out std_logic; -- SDMMC_CCLK
-- hps_io_UART0_RX : in std_logic := 'X'; -- UART0_RX
-- hps_io_UART0_TX : out std_logic; -- UART0_TX
-- hps_io_UART1_RX : in std_logic := 'X'; -- UART1_RX
-- hps_io_UART1_TX : out std_logic; -- UART1_TX
-- hps_io_gpio1_io0 : inout std_logic := 'X'; -- gpio1_io0
-- hps_io_gpio1_io1 : inout std_logic := 'X'; -- gpio1_io1
-- hps_io_gpio1_io4 : inout std_logic := 'X'; -- gpio1_io4
-- hps_io_gpio1_io5 : inout std_logic := 'X'; -- gpio1_io5
-- hps_io_jtag_tck : in std_logic := 'X'; -- jtag_tck
-- hps_io_jtag_tms : in std_logic := 'X'; -- jtag_tms
-- hps_io_jtag_tdo : out std_logic; -- jtag_tdo
-- hps_io_jtag_tdi : in std_logic := 'X'; -- jtag_tdi
-- hps_io_hps_osc_clk : in std_logic := 'X'; -- hps_osc_clk
-- hps_io_gpio1_io19 : inout std_logic := 'X'; -- gpio1_io19
-- hps_io_gpio1_io20 : inout std_logic := 'X'; -- gpio1_io20
-- hps_io_gpio1_io21 : inout std_logic := 'X'; -- gpio1_io21
-- h2f_reset_reset : out std_logic; -- reset
-- f2h_irq1_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
clk_100_clk : in std_logic := 'X'; -- clk
-- emif_hps_pll_ref_clk_clk : in std_logic := 'X'; -- clk
-- emif_hps_oct_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
-- emif_hps_mem_mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
-- emif_hps_mem_mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
-- emif_hps_mem_mem_a : out std_logic_vector(16 downto 0); -- mem_a
-- emif_hps_mem_mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
-- emif_hps_mem_mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
-- emif_hps_mem_mem_bg : out std_logic_vector(0 downto 0); -- mem_bg
-- emif_hps_mem_mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
-- emif_hps_mem_mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
-- emif_hps_mem_mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
-- emif_hps_mem_mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
-- emif_hps_mem_mem_par : out std_logic_vector(0 downto 0); -- mem_par
-- emif_hps_mem_mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
-- emif_hps_mem_mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
-- emif_hps_mem_mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
-- emif_hps_mem_mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
-- emif_hps_mem_mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
button_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
dipsw_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
led_pio_external_connection_in_port : in std_logic_vector(2 downto 0) := (others => 'X'); -- in_port
led_pio_external_connection_out_port : out std_logic_vector(2 downto 0); -- out_port
reset_reset_n : in std_logic := 'X'; -- reset_n
ninit_done_ninit_done : out std_logic -- ninit_done
);
end component qsys_top;
soc_inst : component qsys_top
port map (
-- wd_reset_reset_n => open, -- wd_reset.reset_n
-- agilex_hps_f2h_stm_hw_events_stm_hwevents => stm_hw_events, -- agilex_hps_f2h_stm_hw_events.stm_hwevents
-- agilex_hps_h2f_cs_ntrst => '1', -- agilex_hps_h2f_cs.ntrst
-- agilex_hps_h2f_cs_tck => '1', -- .tck
-- agilex_hps_h2f_cs_tdi => '1', -- .tdi
-- agilex_hps_h2f_cs_tdo => open, -- .tdo
-- agilex_hps_h2f_cs_tdoen => open, -- .tdoen
-- agilex_hps_h2f_cs_tms => '1', -- .tms
-- hps_io_EMAC0_TX_CLK => hps_emac0_TX_CLK, -- hps_io.EMAC0_TX_CLK
-- hps_io_EMAC0_TXD0 => hps_emac0_TXD0, -- .EMAC0_TXD0
-- hps_io_EMAC0_TXD1 => hps_emac0_TXD1, -- .EMAC0_TXD1
-- hps_io_EMAC0_TXD2 => hps_emac0_TXD2, -- .EMAC0_TXD2
-- hps_io_EMAC0_TXD3 => hps_emac0_TXD3, -- .EMAC0_TXD3
-- hps_io_EMAC0_RX_CTL => hps_emac0_RX_CTL, -- .EMAC0_RX_CTL
-- hps_io_EMAC0_TX_CTL => hps_emac0_TX_CTL, -- .EMAC0_TX_CTL
-- hps_io_EMAC0_RX_CLK => hps_emac0_RX_CLK, -- .EMAC0_RX_CLK
-- hps_io_EMAC0_RXD0 => hps_emac0_RXD0, -- .EMAC0_RXD0
-- hps_io_EMAC0_RXD1 => hps_emac0_RXD1, -- .EMAC0_RXD1
-- hps_io_EMAC0_RXD2 => hps_emac0_RXD2, -- .EMAC0_RXD2
-- hps_io_EMAC0_RXD3 => hps_emac0_RXD3, -- .EMAC0_RXD3
-- hps_io_EMAC0_MDIO => hps_emac0_MDIO, -- .EMAC0_MDIO
-- hps_io_EMAC0_MDC => hps_emac0_MDC, -- .EMAC0_MDC
-- hps_io_SDMMC_CMD => hps_sdmmc_CMD, -- .SDMMC_CMD
-- hps_io_SDMMC_D0 => hps_sdmmc_D0, -- .SDMMC_D0
-- hps_io_SDMMC_D1 => hps_sdmmc_D1, -- .SDMMC_D1
-- hps_io_SDMMC_D2 => hps_sdmmc_D2, -- .SDMMC_D2
-- hps_io_SDMMC_D3 => hps_sdmmc_D3, -- .SDMMC_D3
-- hps_io_SDMMC_CCLK => hps_sdmmc_CCLK, -- .SDMMC_CCLK
-- hps_io_UART0_RX => hps_uart0_RX, -- .UART0_RX
-- hps_io_UART0_TX => hps_uart0_TX, -- .UART0_TX
-- hps_io_UART1_RX => hps_uart1_RX, -- .UART1_RX
-- hps_io_UART1_TX => hps_uart1_TX, -- .UART1_TX
-- hps_io_gpio1_io0 => hps_gpio1_io0, -- .gpio1_io0
-- hps_io_gpio1_io1 => hps_gpio1_io1, -- .gpio1_io1
-- hps_io_gpio1_io4 => hps_gpio1_io4, -- .gpio1_io4
-- hps_io_gpio1_io5 => hps_gpio1_io5, -- .gpio1_io5
-- hps_io_jtag_tck => hps_jtag_tck, -- .jtag_tck
-- hps_io_jtag_tms => hps_jtag_tms, -- .jtag_tms
-- hps_io_jtag_tdo => hps_jtag_tdo, -- .jtag_tdo
-- hps_io_jtag_tdi => hps_jtag_tdi, -- .jtag_tdi
-- hps_io_hps_osc_clk => hps_ref_clk, -- .hps_osc_clk
-- hps_io_gpio1_io19 => hps_gpio1_io19, -- .gpio1_io19
-- hps_io_gpio1_io20 => hps_gpio1_io20, -- .gpio1_io20
-- hps_io_gpio1_io21 => hps_gpio1_io21, -- .gpio1_io21
-- h2f_reset_reset => h2f_reset, -- h2f_reset.reset
-- f2h_irq1_irq => f2h_irq1_irq, -- f2h_irq1.irq
clk_100_clk => system_clk_100_internal, -- clk_100.clk
-- emif_hps_pll_ref_clk_clk => emif_hps_pll_ref_clk, -- emif_hps_pll_ref_clk.clk
-- emif_hps_oct_oct_rzqin => emif_hps_oct_oct_rzqin, -- emif_hps_oct.oct_rzqin
-- emif_hps_mem_mem_ck => emif_hps_mem_mem_ck, -- emif_hps_mem.mem_ck
-- emif_hps_mem_mem_ck_n => emif_hps_mem_mem_ck_n, -- .mem_ck_n
-- emif_hps_mem_mem_a => emif_hps_mem_mem_a, -- .mem_a
-- emif_hps_mem_mem_act_n => emif_hps_mem_mem_act_n, -- .mem_act_n
-- emif_hps_mem_mem_ba => emif_hps_mem_mem_ba, -- .mem_ba
-- emif_hps_mem_mem_bg => emif_hps_mem_mem_bg, -- .mem_bg
-- emif_hps_mem_mem_cke => emif_hps_mem_mem_cke, -- .mem_cke
-- emif_hps_mem_mem_cs_n => emif_hps_mem_mem_cs_n, -- .mem_cs_n
-- emif_hps_mem_mem_odt => emif_hps_mem_mem_odt, -- .mem_odt
-- emif_hps_mem_mem_reset_n => emif_hps_mem_mem_reset_n, -- .mem_reset_n
-- emif_hps_mem_mem_par => emif_hps_mem_mem_par, -- .mem_par
-- emif_hps_mem_mem_alert_n => emif_hps_mem_mem_alert_n, -- .mem_alert_n
-- emif_hps_mem_mem_dqs => emif_hps_mem_mem_dqs, -- .mem_dqs
-- emif_hps_mem_mem_dqs_n => emif_hps_mem_mem_dqs_n, -- .mem_dqs_n
-- emif_hps_mem_mem_dq => emif_hps_mem_mem_dq, -- .mem_dq
-- emif_hps_mem_mem_dbi_n => emif_hps_mem_mem_dbi_n, -- .mem_dbi_n
button_pio_external_connection_export => fpga_debounced_buttons, -- button_pio_external_connection.export
dipsw_pio_external_connection_export => fpga_dipsw_pio, -- dipsw_pio_external_connection.export
led_pio_external_connection_in_port => fpga_led_internal, -- led_pio_external_connection.in_port
led_pio_external_connection_out_port => fpga_led_internal, -- .out_port
reset_reset_n => (system_reset_n AND FPGA_TESTIO1), -- reset.reset_n
ninit_done_ninit_done => ninit_done -- ninit_done.ninit_done
);
Then at the end of the compilation, I got this errors,
Error(17045): Input port I of I/O input buffer primitive soc_inst|emif_fm_hps_0|emif_fm_hps_0|arch|arch_inst|bufs_inst|gen_rzqin.ibuf is not connected. It must be driven by a top-level pin.
What is that, actually? Could you please help me on this?
By the way, can some expert from Altera / Intel please provide some example working project that can be built and loaded into the board?
Please help..
Regards
Occasional Contributor
