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nelky's avatar
nelky
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Agilex 7 interface with DDR4

Hi experts, I am using Agilex 7 (AGFB022R25A2I3V). I wish to use the internal bridges to write to and read from DDR4. My idea is like this,... Build a internal connections using Platform Designer...
Board Debug
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Is that an SoC device? Are you talking about the dedicated EMIF for the HPS in an SoC or just a standard EMIF connected to the FPGA? Lots of info available.

EMIF IP user guide: https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/about-the-external-memory-interfaces.html

Example design user guide: https://www.intel.com/content/www/us/en/docs/programmable/683162/23-1-2-7-0/about-the-external-memory-interfaces.html

Training: https://learning.intel.com/developer/learn/courses/89/introduction-to-memory-interfaces-in-intelr-agilex-devices

  • nelky's avatar
    nelky
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi sstrell,

    I have gone through and followed the documents you recommended. Still I still get errors when I tried to generate using Platform Desginer.

    I followed the document to make an EMIF IP and integrate it into the GHRD built from https://www.rocketboards.org/foswiki/Projects/SettingUpAndUsingBridgesOnAgilex

    I still got the error, ...

    HPS_OSC_CLK input is required to drive the main PLL. But the pin has not been specified in the HPS I/O selection.

    Error: clk_100: "Board" (board) "default" is out of range: "Unknown", "Agilex Development Kit", "Arria 10 SoC Development Kit", "Stratix 10 SoC Development Kit", "Unknown"

    I don't know how to solve these errors. Could you please guide me?

    By the way, what's the difference between

    1. External Memory Interfaces for HPS Intel Agilex FPGA IP and

    2. External Memory Interfaces Intel Agilex FPGA IP

    ?

    I can see that #1 has hps_emif conduit while #2 doesn't have. But if you use Hard Processor System Intel Agilex FPGA IP, it has hps_emif. If you use #1, you can connect with the hps_emif together. If you use #2, the hps_emif will have no connection.

    If you follow the attached document, it's guiding you to make #2.

    For read/write with DDR4, which one should be used?

    After the above is built, at the Linux side, how can I write to and read from the DDR4 addresses?

    For this requirement, I can see that there are 2 parts. One at the FPGA and one at the SoC Linux. Do you have the sample of this kind of project?

    Regards