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Nicole04's avatar
Nicole04
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Agilex 5 Unused HSIO Banks

Good day, I would like to confirm that the following statement in Table 13 of the Pin Connection Guidelines: Agilex 5 FPGAs and SoCs document refers to individual banks from the HSIO group: Connect...
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Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi,

The VCCIO_PIO should be connected to GND, 1.0 V, 1.05 V, 1.1 V, 1.2 V, or 1.3 V depending on your future usability. Do not leave it unconnected.


So, if 3B and 2B will be totally unused in future as well, you may consider it connecting to GND to save power.


Regards


  • Nicole04's avatar
    Nicole04
    Icon for Occasional Contributor rankOccasional Contributor
    11 months ago

    If the power pins of bank 3B and 2B are connected to GND, but the 3A and 2A banks are powered, will this cause problems?