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Suresh430's avatar
Suresh430
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2 months ago

Agilex 5 Sulfur Partial Write Issue on F2H ACE‑Lite I/F (256‑bit) with AXI Master of 128‑bit

Hello Intel Support Team, I am working on an Agilex 5 Sulfur Development Board and implementing an HPS‑based design where a USB Host module (custom logic) acts as an AXI Master and performs memory a...
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Suresh430's avatar
Suresh430
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1 month ago

Hi Kian,

              Thanks for your insights. Is there any width adaptor IP readily available with altera to support 128-bit Merging into 256-bit for write channel and 256-bit Splitting into 128-bit for read channel.


Regards
Suresh

KianHinT_altera's avatar
KianHinT_altera
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6 days ago

 

Hi Suresh,

We have not heard from you for sometime, may I know the status for this case?

Otherwise we would like to transition to community support.

 

Thanks

Regards

Kian