Agilex 5 Premium Dev Kit SFP Implementation

Hi everyone,

I’m working on a design that interfaces with the SFP+ cage on the Agilex 5 Premium Dev Kit. My reference point is the Agilex™ 5E HPS Enhanced System Example Design (from the documentation here: https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/premium/egsrd/ug-ehps-agx5e-premium/), which targets the QSFP cage using the GTS hard EMAC/PHY. My goal is to take this same framework and retarget it to the SFP+ cage instead.

Initially I moved the relevant pins and refclock to the SFP+ bank, but I realized that when using transceiver banks on opposite sides of the device, the design requires two GTS Reset Sequencer IPs, as mentioned in the GTS User Guide: “Two GTS Reset Sequencer IP instances if your design uses transceivers on both sides of the device.”
(For now I’m ignoring the SFP+ I2C/I3C management interface — I plan to either route I3C from the HPS to the FPGA or instantiate a soft I2C and add it to the device tree, but first I need to get a clean FPGA build.)

Because the example design uses the HPS USB interface, which resides on the opposite side of the SFP+ bank (4A), I suspected this was part of the issue. However, after attempting a full build, I encounter the following error:

Error(175006): There is no routing connectivity between source IPFLUXTOP_UXTOP_WRAP and the pin

Info(175026): Source: IPFLUXTOP_UXTOP_WRAP soc_inst|cpl_eth_tg_ss_0|intel_eth_gts_0|intel_eth_gts_0|hip_inst|n_channel_superset_wrapper_inst|n_channel_superset|hal_top_wrapper_inst|hal_top_ip|one_lane_inst_0|one_lane_hal_top_p0|gen_non_usb_mode.phy_hal_top_inst|phy_hal_top|phy_hal_coreip_inst|ch4_phy_inst|x_std_ipfluxtop_uxtop_wrap_0

    Info(175013): The IPFLUXTOP_UXTOP_WRAP is constrained to the region (185, 7) to (185, 7) due to related logic

        Info(175015): The I/O pad i_rx_serial_data_n is constrained to the location PIN_BN3 due to: User Location Constraints (PIN_BN3)

        Info(14709): The constrained I/O pad drives this IPFLUXTOP_UXTOP_WRAP

    Info(175021): The source IPFLUXTOP_UXTOP_WRAP was placed in location IPFLUXTOPUXTOPWRAP_X185_Y7_N1962

Error(175022): The pin could not be placed in any location to satisfy its connectivity requirements

Info(175029): 2 locations affected

        Info(175029): BL10

        Info(175029): pin containing PIN_BL7

I’ve been reading that when the HPS subsystem is enabled, Bank 4A becomes constrained due to shared clocking resources between the HPS and the adjacent transceiver banks, potentially limiting available routing/placement options.

Has anyone encountered similar issues when targeting the SFP+ cage or using GTS transceivers on the 4A side with HPS enabled? Any insight or guidance would be greatly appreciated.

Thank you!