New Contributor
New ContributorHi,
an SDR (I/O) fast clock of 504MHz is not covered by the Data Sheet.
I used a small demo implementation to figure is 504MBit feasible via I/O (without dedicated SERDES) and I have the strong feeling that the STA is doing a very pessimistic timing analysis.
Both paths (Arrival and required) have the same clock source (outclk(0) of the PLL) and in my opinion up to this point it is the 'same internal wire' due we are talking about physical clock networks inside the FPGA.
Why is the timing estimation for both path up to Line 16 not the same?
Why is there a WC analysis beginning at the Input ref clock of the PLL?
In earlier days we had somethng like 'clock-path-pessimism-removal'.
Any Explanation?
