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TK99's avatar
TK99
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11 months ago

Agilex 5 LVDS Serdes (Serdes factor 7 and 504Mbit/s valid?)

Hello, I used A10 and C10GX devices to implement a LVDS Serdes with 504MBit/s and a 1:7 ratio. This is common interface towards LCD Panels (HD). We are looking forward to use an Agilex 5 device f...
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TK99's avatar
TK99
Icon for New Contributor rankNew Contributor
11 months ago

Hi,

Thank you for your reply!

I need an 504MBit/s LVDS output (4 lanes and one for clock 504MBit/7).

For Arria10, Cyclone 10 GX and Agilex 7 were are LVDS Serdes Specs available to support this feature with a Serdes factor of 7 (internal clockrate 504/7) and a wide range regarding speed.

Right, the internal core frequency can be quite high for the A5.

But, The AC timing spec for Agilex5 has only Serdes factor of 4 or 8 and starting from 600Mbit/s (external).

The Spec for the DDR (Serdes Factor 2) Performance is given by 500Mbit (not 504)

The Agilex 5 LVDS Serdes Datasheet looks different to the Arria10, Agilex 7.

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
11 months ago
Hi,
you won't necessarily use DDR register for the SERDES design. I presume that a SDR fast clock of 504 MHz and slow clock of 72 MHz will be PLL generated and SERDES implemented in registers.