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TK99's avatar
TK99
Icon for New Contributor rankNew Contributor
11 months ago

Agilex 5 LVDS Serdes (Serdes factor 7 and 504Mbit/s valid?)

Hello, I used A10 and C10GX devices to implement a LVDS Serdes with 504MBit/s and a 1:7 ratio. This is common interface towards LCD Panels (HD). We are looking forward to use an Agilex 5 device f...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
11 months ago
Hi,
if it's only LVDS TX (no CDR involved), SERDES can be easily implemented in FPGA fabric, Agilex 5 is fast enough, maximum core clock is 780 MHz for lowest speed grade. There might be other options, but your spec isn't completely clear for me.