Forum Discussion
TK99
New Contributor
New ContributorAgilex 5 LVDS Serdes (Serdes factor 7 and 504Mbit/s valid?)
Hello, I used A10 and C10GX devices to implement a LVDS Serdes with 504MBit/s and a 1:7 ratio. This is common interface towards LCD Panels (HD). We are looking forward to use an Agilex 5 device f...
FvM
Super Contributor
Super ContributorHi,
if it's only LVDS TX (no CDR involved), SERDES can be easily implemented in FPGA fabric, Agilex 5 is fast enough, maximum core clock is 780 MHz for lowest speed grade. There might be other options, but your spec isn't completely clear for me.
if it's only LVDS TX (no CDR involved), SERDES can be easily implemented in FPGA fabric, Agilex 5 is fast enough, maximum core clock is 780 MHz for lowest speed grade. There might be other options, but your spec isn't completely clear for me.
